Time-interleaved pulse-shrinking time-to-digital converter with reduced conversion time

A silicon-efficient time-interleaved pulse-shrinking time-to-digital converter (TDC) is proposed. The proposed TDC consists of a 16-stage coarse pulse-shrinking TDC with constant per-stage shrinkage 4.8 ns and a pair of 16-stage fine pulse-shrinking TDCs operated in a time-interleaved manner with constant per-stage shrinkage 296 ps. A simple residual time extraction method is proposed to extract the residual pulse of the coarse TDC simultaneously with digitization carried out by the TDC so that the digitization can be carried out by both the coarse and fine TDCs simultaneously to minimize conversion time. The characteristics of the proposed TDC including silicon consumption, power consumption, conversion time, jitter, and mismatch-induced timing errors are investigated. The proposed TDC was implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results show that the TDC offers 0.296–76.8 ns dynamic range, 850 ps conversion time, 0.285 LSB differential nonlinearity, and 0.78 LSB integral nonlinearity while consuming 7 mW.