Self-timed is self-checking |
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Authors: | Ilana David Ran Ginosar Michael Yoeli |
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Affiliation: | (1) Department of Electrical Engineering, Technion-Israel Institute of Technology, 32000 Haifa;(2) Department of Electrical Engineering and Department of Computer Science, Technion-Israel Institute of Technology, 32000 Haifa;(3) Department of Computer Science, Technion-Israel Institute of Technology, 32000 Haifa |
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Abstract: | Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, andundefined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete self-checking property; further, the circuit is guaranteed to never generate a legal but erroneous output if it contains a fault. Minimal hardware is needed to detect that a circuit has either halted or has generated an illegal output. |
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Keywords: | asynchronous systems combinational logic finite state machines self-checkings self-timed |
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