| 一种融合FPGA和ISS技术的软硬件协同验证方法 |
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| 引用本文： | 王培东,李锋伟,杨俊成. 一种融合FPGA和ISS技术的软硬件协同验证方法[J]. 计算机工程与应用, 2009, 45(30): 73-75. DOI: 10.3778/j.issn.1002-8331.2009.30.022 |
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| 作者姓名： | 王培东 李锋伟 杨俊成 |
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| 作者单位： | 哈尔滨理工大学,计算机科学与技术学院,哈尔滨,150080;长春工业大学,计算机科学与技术学院,长春,130012 |
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| 摘 要： | 建立了一种基于硬件加速器FPGA 和指令集模拟器ISS对嵌入式系统功能进行软硬件协同验证的方法。针对此方法的实现，分析了协同验证过程中软硬件交互技术，并给出总线功能模型BFM结构及其实现方法。经实例验证分析表明，基于FPGA和ISS的协同验证方法，在对嵌入式应用系统验证中与其他几种常用方法比较具有较明显的优势。
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| 关 键 词： | 软硬件协同验证 现场可编程门阵列 指令集模拟器 总线功能模型 |
| 收稿时间： | 2008-09-08 |
| 修稿时间： | 2008-12-11 |
Hardware/Software co-verification solution integrated FPGA and ISS |
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| WANG Pei-dong,LI Feng-wei,YANG Jun-cheng. Hardware/Software co-verification solution integrated FPGA and ISS[J]. Computer Engineering and Applications, 2009, 45(30): 73-75. DOI: 10.3778/j.issn.1002-8331.2009.30.022 |
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| Authors: | WANG Pei-dong LI Feng-wei YANG Jun-cheng |
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| Affiliation: | 1.College of Computer Science，Harbin University of Science and Technology，Harbin 150080，China 2.College of Computer Science and Engineering，Changchun University of Technology，Changchun 130012，China |
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| Abstract: | This paper establishes a hardware-software co-verification solution for embedded systems，which is based on fast prototyping FPGA and Instruction Set Simulator（ISS）.For this method of achieving，analysis of the co-verification process of interactive software and hardware technology，and gives Bus Functional Model（BFM） structure and method.As an example of that the co-verification solution based on FPGA and ISS takes a clear advantage compared with several other commonly used verification system for embedded applications. |
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| Keywords: | Hardware/Software co-verification Field Programmable Gate Array（FPGA） Instruction Set Simulator（ISS） Bus Functional Model（BFM） |
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