Reversible energy recovery logic circuit without non-adiabaticenergy loss |
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Authors: | Joonho Lim Kipaek Kwon Soo-Ik Chae |
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Affiliation: | Sch. of Electr. Eng., Seoul Nat. Univ.; |
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Abstract: | The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, which consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits |
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