| 基于电路裁剪的统计时钟偏差估计方法 |
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| 引用本文： | 方君,陆伟成,赵文庆.基于电路裁剪的统计时钟偏差估计方法[J].微电子学,2007,37(5):632-635. |
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| 作者姓名： | 方君 陆伟成 赵文庆 |
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| 作者单位： | 复旦大学,专用集成电路与系统国家重点实验室,上海,201203 |
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| 基金项目： | 国家自然科学基金;国家重点基础研究发展计划(973计划);教育部跨世纪优秀人才培养计划;高等学校博士学科点专项科研项目;上海市自然科学基金;上海市应用材料研究与发展项目 |
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| 摘 要： | 随着集成电路特征尺寸的不断缩小,工艺偏差引起时钟偏差的不确定性,导致时钟偏差呈现出一定的统计特性。分析了哪些时钟路径可能会成为最长、最短路径,提出了一种基于电路裁剪的统计时钟偏差估计方法,可以快速估计时钟偏差的统计特性。实验结果表明,提出的算法可以在很小的精度损失下提高电路模拟的速度。
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| 关 键 词： | 工艺偏差 时钟偏差 电路裁剪 |
| 文章编号： | 1004-3365（2007）05-0632-04 |
| 修稿时间： | 2007-02-27 |
Statistical Clock Skew Estimation Method Based on Circuit Truncation |
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| FANG Jun,LUK Wai-Shing,ZHAO Wen-qing.Statistical Clock Skew Estimation Method Based on Circuit Truncation[J].Microelectronics,2007,37(5):632-635. |
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| Authors: | FANG Jun LUK Wai-Shing ZHAO Wen-qing |
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| Abstract: | With shrinking IC feature size,clock skew uncertainty due to process variations would lead to particular statistical characteristics.Clock paths that were most likely to become the longest or shortest were analyzed,and a statistical clock skew estimation method based on circuit truncation was proposed.Experimental results showed that the proposed method could effectively improve simulation speed at the expense of just a little loss of accuracy. |
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| Keywords: | Process variations Clock skew Circuit truncation |
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