| 基于QuartusⅡ9.0的时序逻辑电路设计 |
| |
| 引用本文： | 黄聚义,任剑,张洪群. 基于QuartusⅡ9.0的时序逻辑电路设计[J]. 仪表技术, 2014, 0(6): 43-44 |
| |
| 作者姓名： | 黄聚义 任剑 张洪群 |
| |
| 作者单位： | 海军航空工程学院青岛校区,山东青岛266041 |
| |
| 摘 要： | 研究了基于QuartusⅡ9.0软件的时序逻辑电路设计方法,其中程序设计法采用了Verilog HDL语言。以同步4位二进制可逆计数器为例演示了设计过程,并对设计情况进行了功能仿真,验证了设计的正确性。
|
| 关 键 词： | QuartusⅡ. 可逆计数器 功能仿真 |
Design of Sequential Logical Circuit Based on Proteus |
| |
| HUANG Ju,yi,REN Jian,ZHANG Hong-qun. Design of Sequential Logical Circuit Based on Proteus[J]. Instrumentation Technology, 2014, 0(6): 43-44 |
| |
| Authors: | HUANG Ju yi REN Jian ZHANG Hong-qun |
| |
| Affiliation: | ( Naval Aeronautical Engineering Academy, Qingdao Branch, Qingdao 266041, China) |
| |
| Abstract: | The article studied design method of sequential logic circuit based on Quartus Ⅱ 9. 0 software,which adopted the Verilog HDL language programming method. It takes the synchronous 4 bit binary reversible counter as an example to illustrate the design process. And the design of the function simulation verifies the correctness of the design. |
| |
| Keywords: | QuartusⅡ9.0 forward-backward counter functional simulation |
| 本文献已被 CNKI 维普 等数据库收录！ |
|
