| 基于FPGA实现RS编码新型方案 |
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| 引用本文： | 顾嘉辉,侯永彬.基于FPGA实现RS编码新型方案[J].通信技术,2011,44(5):15-18. |
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| 作者姓名： | 顾嘉辉 侯永彬 |
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| 作者单位： | 1. 西安电子科技大学ISDN国家重点实验室,陕西,西安,710071
2. 中国电子科技集团第54研究所,河北,石家庄,050081 |
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| 摘 要： | 针对目前通讯大量差错控制的需要,提出一种利用现场可编程门陈列（FPGA）内核实现RS编码与交织的新型方案。通过控制RS编码数据流的输入与输出,完成对异步数据的整帧处理,利用多级流水实现数据的实时传输。通过对交织块RAM的读写地址的控制,同步完成任意深度的交织操作。工程实践表明,该方案在上下行链路中快速稳定的实现了RS编码与交织,并适应多种差错控制编码格式的要求。与常规方法相比,有效降低了信道编码工程实现复杂度和对FPGA芯片等硬件的要求。
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| 关 键 词： | 差错控制 现场可编程门陈列 块状RAM RS编码与交织 |
New Method for Realizing RS Encode based on FPGA |
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| GU Jia-hui,HOU Yong-bin.New Method for Realizing RS Encode based on FPGA[J].Communications Technology,2011,44(5):15-18. |
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| Authors: | GU Jia-hui HOU Yong-bin |
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| Affiliation: | ②(①State Lab.of ISDN Xidian Univ,Xi＇an Shaanxi 710071,China; ②No.54 Research Institution of China Electronics Technology Co.,Shijiazhuang Hebei 050081,China) |
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| Abstract: | The new method of RS encode and interweave by using the IP-core of the FPGA is proposed,aiming at satisfying the needs of the widely-used error control technology in the communication field at present.By controlling the in-data stream and out-data stream,the asynchronous process of the whole frame is accomplished,while by using multi-level pipeline,the real-time transfer of the data is achieved.By controlling the read-address and write-address of the block RAM,the interleaving operation of the arbitrary dep... |
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| Keywords: | control of the error FPGA block RAM Rs encode and interleaving |
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