Test generation algorithm for analog systems based on support vector machine |
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Authors: | Ting Long Houjun Wang Bing Long |
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Affiliation: | (1) Electrical engineering department, ?cole Polytechnique de Montr?al, C.P. 6079, succ. Centre-Ville, Montr?al, Qu?bec, Canada, H3C 3A7 |
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Abstract: | In some methods for test generation, an analog device under test (DUT) is treated as a discrete-time digital system by placing
it between a digital-to-analog converter and an analog-to-digital converter. Then the test patterns and responses can be performed
and analyzed in the digital domain. We propose a novel test generation algorithm based on a support vector machine (SVM).
This method uses test patterns derived from the test generation algorithm as input stimuli, and sampled output responses of
the analog DUT for classification and fault detection. The SVM is used for classification of the response space. When the
responses of normal circuits are similar to those of faulty circuits (i.e., the latter have only small parametric faults),
the response space is mixed and traditional algorithms have difficulty in distinguishing the two groups. However, the SVM
provides an effective result. This paper also proposes an algorithm to calculate the test sequence for input stimuli using
the SVM results. Numerical experiments prove that this algorithm can enhance the precision of test generation. |
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