Structural Fault Based Specification Reduction for Testing Analog Circuits |
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Authors: | Soon-Jyh Chang Chung Len Lee Jwu E. Chen |
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Affiliation: | (1) Department of Electronic Engineering & Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, Republic of China;(2) Department of Electrical Engineering, Chung-Hua University, Hsin-Chu, Taiwan, Republic of China |
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Abstract: | Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach. |
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Keywords: | analog test test cost reduction specification-based test fault-based test |
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