基于FPGA时域有限差分算法的设计与实现

以时域有限差分法的二维形式为例,用Verilog HDL语言加以实现.采用32位单精度浮点数进行加减法和乘法运算,以保证计算的精度.通过modelsim软件仿真,以Altera FPGA的硬件实现来确保设计的正确性.实验结果显示,基于FPGA的时域有限差分法硬件实现方法对提高速度效果明显,是提高算法性能的有效途径.

An FPGA Implementation of Finite Difference Time Domain Algorithm

Finite difference time Domain algorithm is a popular algorithm in the computation electromagnetic.However,the huge computing capacity is a limiting factor for its applications.This paper presents implementation of the 2D FDTD algorithm by FPGA whose circuit is described by the verilog HDL.32 Bit single-precision floating-point specification is adopted to ensure the accuracy of calculation.After the Modelsim software simulation,the correctness of the design is ensured by the hardware implementation of Altera FPGA.The experimental results show that FPGA implementation speeds up the algorithm greatly.Thus,it becomes an effective way to improve the performance of FDTD algorithm.