| 双通道数字脉冲压缩的FPGA实现 |
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| 引用本文： | 赵菁菁,蒋留兵,鲍胜荣.双通道数字脉冲压缩的FPGA实现[J].现代雷达,2008,30(4):72-74. |
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| 作者姓名： | 赵菁菁 蒋留兵 鲍胜荣 |
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| 作者单位： | 1. 南京电子技术研究所,南京,210013
2. 桂林电子科技大学信息与通信学院,桂林,541004 |
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| 摘 要： | 脉冲压缩是雷达信号处理的重要组成部分,用FPGA实现硬件数字脉压是当前脉压技术的发展方向。阐述了一种基于FPGA的双通道数字脉冲压缩系统的原理,方案与具体实现技术,分析了其性能。工程实践表明,与传统的方法相比,该实现方法在通用性,实时性上都具有很强的优越性和推广应用前景。
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| 关 键 词： | 数字脉冲 脉冲压缩 现场可编程门阵列 |
| 修稿时间： | 2007年12月29 |
Realization of Dual Channels Digital Pulse Compression by FPGA |
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| ZHAO Jing-jing,JIANG Liu-bing,BAO Sheng-rong.Realization of Dual Channels Digital Pulse Compression by FPGA[J].Modern Radar,2008,30(4):72-74. |
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| Authors: | ZHAO Jing-jing JIANG Liu-bing BAO Sheng-rong |
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| Abstract: | Pulse compression is the key part of radar signal processing.The realization of digital pulse compression by FPGA is the current of technology progression.In this paper,the theory,design and realization of dual channels digital pulse compression based on the FPGA is studied,the performance of this scheme is analyzed.It is shown by engineer practice that this scheme has very strong superiority on real time performance,generality and than conventional method and it has a bright application prospect. |
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| Keywords: | digital pulse pulse compression FPGA |
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