| 一种改进的高速高精度ADC数字校准算法 |
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| 引用本文： | 青山,李广军,李儒章. 一种改进的高速高精度ADC数字校准算法[J]. 微电子学, 2014, 0(1): 118-122 |
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| 作者姓名： | 青山 李广军 李儒章 |
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| 作者单位： | 电子科技大学 通信与信息工程学院, 成都 611731;电子科技大学 通信与信息工程学院, 成都 611731;模拟集成电路重点实验室, 重庆 400060 |
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| 基金项目： | 中央高校基本科研业务费专项资金资助项目。 |
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| 摘 要： | 提出一种能快速收敛并具有鲁棒性的流水线模数转换器(ADC)数字校准方法。设计的ADC采用12级1.5位/级MDAC和一个6位高精度SAR ADC的结构。采用Altera FPGA,对该算法进行了验证。结果表明,用该方法校准的A/D转换器,在90.55 MHz输入频率下,SNDR可达到84 dB,DNL为-0.59/0.28 LSB,INL为-0.59/0.34 LSB。
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| 关 键 词： | A/D转换器 数字校准算法 盲均衡 |
An Improved Digital Calibration Algorithm for High Speed and High Resolution Analog-to-Digital Converter |
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| QING Shan,LI Guangjun and LI Ruzhang. An Improved Digital Calibration Algorithm for High Speed and High Resolution Analog-to-Digital Converter[J]. Microelectronics, 2014, 0(1): 118-122 |
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| Authors: | QING Shan LI Guangjun LI Ruzhang |
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| Affiliation: | School of Communication and Information Engineering, Univ.of Electronic Science and Technology of China, Chengdu 611731, P.R.China;School of Communication and Information Engineering, Univ.of Electronic Science and Technology of China, Chengdu 611731, P.R.China;Science and Technology on Analog Integrated Circuits, Chongqing 400060, P.R.China |
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| Abstract: | A fast convergent digital calibration algorithm with robustness for pipeline analog-to-digital converter (ADC) was presented. In this structure, 12 stages of MDAC with 1.5-bit/stage and a 6-bit SAR backend ADC were adopted. The proposed calibration approach was verified on FPGA, which achieved an SNDR of 84 dB, a DNL of -0.59/0.28 LSB, and an INL of -0.59/0.34 LSB at 90.55 MHz input frequency. |
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| Keywords: | A/D converter Digital calibration algorithm Blind-LMS |
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