The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.