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基于多核处理器BWDSP1042的FFT性能优化
引用本文:蔺丽华,李 敏,苏 涛,张美春,王佳仪. 基于多核处理器BWDSP1042的FFT性能优化[J]. 电讯技术, 2021, 61(6): 759-764. DOI: 10.3969/j.issn.1001-893x.2021.06.016
作者姓名:蔺丽华  李 敏  苏 涛  张美春  王佳仪
作者单位:西安科技大学通信与信息工程学院,西安710054;西安电子科技大学雷达信号处理国家重点实验室,西安710126
基金项目:国家科技重大专项(2012ZX01034001-001)
摘    要:博微DSP1042(BWDSP1042)是我国自主研发的一款高性能数字信号处理器.现阶段,由于BWDSP硬件计算资源和访存带宽限制,通过调优快速傅里叶变换(Fast Fourier Transform,FFT)算法结构运算时间仍可减少.基于高性能多核BWDSP1042体系架构以及指令编排原则,优化了基-2FFT算法结构...

关 键 词:数字信号处理  BWDSP1042  快速傅里叶变换  运算时间

Optimization of FFT performance based on BWDSP1042
LIN Lihu,LI Min,SU Tao,ZHANG Meichun,WANG Jiayi. Optimization of FFT performance based on BWDSP1042[J]. Telecommunication Engineering, 2021, 61(6): 759-764. DOI: 10.3969/j.issn.1001-893x.2021.06.016
Authors:LIN Lihu  LI Min  SU Tao  ZHANG Meichun  WANG Jiayi
Abstract:Bo Wei DSP1042(BWDSP1042) is a high-performance digital signal processor independently developed by China.At present,due to the limitations of BWDSP hardware computing resources and memory access bandwidth,the calculation time can still be reduced by tuning the fast Fourier transform(FFT) algorithm structure.This paper optimizes the radix-2 FFT algorithm structure based on the high-performance multi-core BWDSP1042 architecture and instruction scheduling principles.While making full use of hardware resources,the calculation time of the FFT algorithm is reduced.Matlab program is used to verify the correctness of the FFT assembly algorithm,and it is compared with the actual operating cycle of the FFT algorithm in the BWDSP100 and C6678 function libraries.The research results show that the calculation time of the 512-point,1 024-point,and 2 048-point fixed-point complex FFT algorithm is more than twice as fast as the FFT in the BWDSP100 library and the FFT in the C6678 library.
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