| 基于PD SOI的GCNMOS电源箝位保护电路 |
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| 引用本文： | 王忠芳,谢成民,赵德益,吴龙胜,刘佑宝.基于PD SOI的GCNMOS电源箝位保护电路[J].武汉大学学报(工学版),2011,44(2):245-248. |
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| 作者姓名： | 王忠芳 谢成民 赵德益 吴龙胜 刘佑宝 |
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| 作者单位： | 西安微电子技术研究所研究生部,陕西,西安,710054 |
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| 摘 要： | 随着绝缘体上硅(SOI)技术的快速进展,SOI集成电路的静电放电(ESD)保护已成为一个主要的可靠性问题.研究了基于PD SOI工艺的栅耦合N型金属氧化物半导体管(GCNMOS)电源箝位保护电路,以形成全芯片ESD保护网络.利用HSPICE仿真的方法,可以准确地确定R值和C值,以确定合理的触发电压.根据PD SOI工艺特点设计了基于不同体偏置类型、不同源漏注入类型和不同栅宽的NMOS管的各种GCNMOS电源箝位保护电路,并进行了MPW流片及TLP测试分析,得到源漏深注、体悬浮的H型栅NMOS组成的GCN MOS电源箝位保护电路的抗ESD能力最好,单位宽度(1μm)抗HBM ESD能力可达9.25 V.
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| 关 键 词： | 静电放电(ESD) 部分绝缘体上硅(PD SOI) 栅耦合NMOS 电源箝位 保护电路 |
Gate coupled NMOS power clamp protection circuit based on PD SOI technology |
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| WANG Zhongfang,XIE Chengmin,ZHAO Deyi,WU Longsheng,LIU Youbao.Gate coupled NMOS power clamp protection circuit based on PD SOI technology[J].Engineering Journal of Wuhan University,2011,44(2):245-248. |
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| Authors: | WANG Zhongfang XIE Chengmin ZHAO Deyi WU Longsheng LIU Youbao |
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| Affiliation: | WANG Zhongfang,XIE Chengmin,ZHAO Deyi,WU Longsheng,LIU Youbao(Department of Graduate,Xi'an Microelectronics Technology Institute,Xi'an 710054,China) |
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| Abstract: | With the quick development of silicon-on-insulator(SOI) technology,electro static dischargs(ESD) protection of SOI integrated circuit is becoming a major reliability issue.In order to form whole-chip ESD protection network,this paper investigates the gate coupled N metal oxide semiconductor(GCNMOS) power clamp protection circuit based on partially depleted(PD) SOI technology.The values of resistance and capacitance can be accurately determined by HSPICE simulation method so that the gate voltage of NMOS can... |
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| Keywords: | electro static discharge partially depleted silicon on insulator gate coupled N metal oxide semiconductor power clamp protection circuit |
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