Simulink behavioral modeling of a 10-bit pipelined ADC |
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Authors: | Samir Barra Souhil Kouda Abdelghani Dendouga N. E. Bouguechal |
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Affiliation: | 1706. Advanced Electronics Laboratory, Department of Electronics, University of Batna, Avenue Chahid Boukhlouf Mohamed El Hadi, 05000, Batna, Algeria 2706. Department of electronics, University of M’sila, M’sila, Algeria 3706. Microelectronics and Nanotechnology Division, August 20 1956 City, Center for Development of Advanced Technologies, BP 17, Baba Hassen, Algiers, Algeria
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Abstract: | The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements. |
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Keywords: | Behavioral modeling analog to digital converters (ADCs pipelined ADC multiple digital to analog converter (MDAC sample and hold (S/H |
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