| 一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计 |
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| 引用本文： | 李政,张盛,刘萌萌,杨津,林孝康. 一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计[J]. 电路与系统学报, 2012, 0(1): 1-4 |
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| 作者姓名： | 李政 张盛 刘萌萌 杨津 林孝康 |
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| 作者单位： | 清华大学深圳研究生院;清华大学微纳电子系 |
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| 基金项目： | 国家863项目,名称:超宽带SoC芯片设计及组网试验(2007AA01Z2B32) |
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| 摘 要： | 本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。
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| 关 键 词： | 低功耗 高线性度缓冲器 折叠 电流插值 超宽带接收机 |
A low power 1G-samples/s,6-bit folded interpolation ADC integrated circuit design |
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| LI Zheng,ZHANG Sheng,LIU Meng-meng,YANG Jin,LIN Xiao-kang. A low power 1G-samples/s,6-bit folded interpolation ADC integrated circuit design[J]. Journal of Circuits and Systems, 2012, 0(1): 1-4 |
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| Authors: | LI Zheng ZHANG Sheng LIU Meng-meng YANG Jin LIN Xiao-kang |
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| Affiliation: | 1(1.Tsinghua Graduate School,Shenzhen,Shenzhen 518055,China; 2.Department of Microelectronics and Nanoelectronices,Beijing 100084,China) |
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| Abstract: | A high-linearity folded interpolation anolog-to-digital converter(ADC) is proposed,which has less area and lower power consumption than high-speed full-parallel ADC(Flash ADC),suitable for low-power ultra-wideband(UWB) receiver.All parts of this circuit are designed,and the layout design and post simulation are performed with SMIC 0.18μm process.Layout core area(without pads) is only 0.45mm2.The total power consumption is only 57mW at the sample rate of 1G samples/s and input signal frequency of 488.77MHz,and the effective number of bits(ENOB) achieves 5.74 bits. |
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| Keywords: | low power high-linearity buffer folded current interpolation ultra-wideband receiver |
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