| 基于FPGA的HDLC协议实现 |
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| 引用本文： | 刘岩俊, 闫海霞, 何昕,. 基于FPGA的HDLC协议实现[J]. 电子器件, 2009, 32(3): 707-710 |
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| 作者姓名： | 刘岩俊 闫海霞 何昕 |
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| 作者单位： | 中国科学院长春光学精密机械与物理研究所,长春,130033;吉林大学电子学院,长春,130012 |
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| 摘 要： | 为了实现高速串行通讯,设计了基于FPGA的RS485总线的通讯接口,FPGA与DSP之间采用双FIFO进行数据缓存,并且通过DSP总线与DSP进行数据交换;开发了以FPGA和DSP为核心的原理图与印制电路板,使用VHDL语言开发了HDLC通讯协议的控制时序.实验结果表明:系统的持续存储速度可以达到1 Mbit/s,工作稳定可靠,没有丢帧、串帧等丢失数据现象.
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| 关 键 词： | FPGA RS485 DSP HDLC |
Implementation of HDLC Protocol Based on FPGA |
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| LIU Yanjun,YAN Haixi,HE Xin. Implementation of HDLC Protocol Based on FPGA[J]. Journal of Electron Devices, 2009, 32(3): 707-710 |
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| Authors: | LIU Yanjun YAN Haixi HE Xin |
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| Affiliation: | LIU Yanjun1,YAN Haixia2,HE Xin1.Changchun Institute of Optics,Fine Mechanics , Physics,Chinese Academy of Sciences,Changchun 130033,China,2.JiLin University Electronic Department,Changchun 130012 |
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| Abstract: | In order to implement high speed serial communication, a communication interface of RS485 bus is designed based on FPGA. Between FPGA and DSP, there are two FIFO cache, the communication data are exchanged by DSP data bus. The PCB card which is centered by the DSP and FPGA, and programs the HDLC protocol with VHDL are designed. Experiment results show that the communication speed can reach 1 Mbit/s, and the system works stable without error. |
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| Keywords: | FPGA RS485 DSP HDLC |
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