FCT6芯片的内建自测试方法

ＦＣＴ６芯片是一个集成了Ｉｎｔｅｌ８０３１微处理器及一些外围电路的嵌入式微控制器，它的集成度和复杂度高，又有嵌入式ＲＡＭ部件，而且芯片管脚数相对较少，必须要有一定的可测试性设计来简化测试代码，提高故障覆盖率。简要讨论了ＦＣＴ６芯片的以自测试为核心的可测试性设计框架，着重介绍了内建自测试的设计与实现，即：芯片中控制器ＰＬＡ和内嵌ＲＡＭ结构的内建自测试设计。测试代码开发过程中的仿真结果表明，这些可测试

On the Design of Built-in Self-Test Circuits in FCT6

We developed an ASIC chip FCT6 for flight control of a certain type of aeroplane. This chip integrated an 8 bit microcontroller, an embedded RAM and some peripheral components. In such a chip, testability design is necessary for simplifying test pattern generation, and decreasing test complexity. This paper describes its Built In Self Test(BIST) design and implementation. Fig.1 shows the architecture of FCT6. In section 2, we discuss the design of BIST circuits in detail, figures 3 and 4 show the function diagram of BIST for programmable logic arrays (PLA) and embedded RAM respectively. Table 2 gives the area cost of these BIST circuits, it shows that all BIST circuits occupy only 4.8% of the overall chip area. Table 3 gives the fault simulation results of a test program with 860 instructions for each module in FCT6. It shows that 90% of all the faults have been covered.