| 基于PCI总线的高速数据采集系统的研究 |
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| 引用本文： | 程玉,祖传友. 基于PCI总线的高速数据采集系统的研究[J]. 湖北工业大学学报, 2003, 18(4): 51-53 |
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| 作者姓名： | 程玉 祖传友 |
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| 作者单位： | 湖北工学院电气技术与计算机科学系,湖北,武汉,430068 |
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| 摘 要： | 介绍了一种基于PCI总线的数据采集卡的设计思想和实现方案．本方案用两路低速A／D合成一路高速A／D，提高了工作的可靠性．应用CPLD技术实现PCI总线接口，并从状态机方面详细地介绍了PCI总线接口设计的时序控制．
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| 关 键 词： | PCI总线 高速数据采集系统 A／D转换器 CPLD 接口 时序控制 分时存储 复杂可编程逻辑器件 |
| 文章编号： | 1003-4684(2003)08-0051-03 |
| 修稿时间： | 2002-11-19 |
Research of High Speed Data Acquisition System Based on PCI Bus |
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| CHENG Yu,ZU Chuan-you Dep. of Electrical Engin. , Computer Sci.,Hubei Polytechnic Univ.,Wuhan ,China. Research of High Speed Data Acquisition System Based on PCI Bus[J]. Journal of Hubei University of Technology, 2003, 18(4): 51-53 |
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| Authors: | CHENG Yu ZU Chuan-you Dep. of Electrical Engin. & Computer Sci. Hubei Polytechnic Univ. Wuhan China |
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| Affiliation: | CHENG Yu,ZU Chuan-you Dep. of Electrical Engin. & Computer Sci.,Hubei Polytechnic Univ.,Wuhan 430068,China |
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| Abstract: | This paper presents a design idea and realized plan based on high_speed data acquisition. Thescheme of two_channel synthesis to implement high speed A/D conversion with lower speed A/D conver-sion enhances the system reliability. The order control of PCI Bus interface designed is illustrated detailedby the application of CPLD technology to PCI Bus interface. |
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| Keywords: | data acquisition A/D conversion PCI bus interface complex programmable logic device |
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