| 基于FPGA的高速数字下变频系统设计 |
| |
| 引用本文： | 朱刘松,邢立冬. 基于FPGA的高速数字下变频系统设计[J]. 国外电子元器件, 2013, 0(23): 117-119 |
| |
| 作者姓名： | 朱刘松 邢立冬 |
| |
| 作者单位： | [1]解放军第323医院网络中心陕西西安710054 [2]西安邮电大学电子工程学院陕西西安710121 |
| |
| 摘 要： | 基于FPGA设计了一高速数字下变频系统,在设计中利用并行NCO和多相滤波相结合的方法有效的降低了数据的速率,以适合数字信号处理器件的工作频率.为了进一步提高系统的整体运行速度,在设计中大量的使用了FPGA中的硬核资源DSP48.Xilinx ISE14.4分析报告显示,电路工作速度可达360MHz.最后给出了在Matlab和ModelSim中仿真的结果,验证了各个模块以及整个系统的正确性.
|
| 关 键 词： | 数字下变频 并行NCO 多相滤波 DSP48 |
High-speed digital down-convertor design based on FPGA |
| |
| ZHU Liu-song,XING Li-dong. High-speed digital down-convertor design based on FPGA[J]. International Electronic Elements, 2013, 0(23): 117-119 |
| |
| Authors: | ZHU Liu-song XING Li-dong |
| |
| Affiliation: | 1. The 323rd Hospital of PLA , Xi＇ an 710054, China; 2. Xi＇an university of Posts and Telecommunications, Xi ＇an 710121, China) |
| |
| Abstract: | A high-speed digital down conversion system design method based on FPGA was introduced in this paper. The design combined parallel NCO technology with polyphase filter, which greatly reduces the data rate to suit the digital signal processing devices operating frequency .To further improve the system＇s overall speed, DSP 48 hard cores were widely used in the design. The synthesis report of Xilinx ISE 14.4 show that the operating frequency of the circuit can up to 360MHz or more. Finally, both the Matlab and the ModelSim simulation results show that the system successfully realizes functions of digital down-convertor. |
| |
| Keywords: | digital down-convertor parallel NCO polyphase filter DSP48 |
| 本文献已被 维普 等数据库收录！ |
