基于逻辑门类型的老化路径约减算法

随着CMOS集成电路工艺尺寸的不断缩小,电路可靠性问题日益严重,而由NBTI效应引起的电路老化问题尤其突出。由于实际电路大多比较复杂,路径较多,如果对所有路径进行老化预测,工作量会非常大。针对这一实际难题提出了一种基于电路路径中门种类和数目的迭代算法,用来划分和约减电路中不受老化影响电路功能的电路路径。该方法根据路径中每类门的数目和门种类对电路老化的不同影响程度将电路路径进行分类,约减掉不需要预测老化的路径,减少了老化预测的工作量,提高了电路老化预测的效率。

Aging Path Reduction Algorithm for Type of Logic Gates

As decrease of CMOS technology scaling of integrated circuit,the problems of circuit reliability are more serious,and the circuit aging caused by NBTI is especially conspicuous.In fact,most of circuits are complicated and there are many paths in a circuit.The workload will be large if we predict aging of all paths.In this work,we proposed an iterative algorithm based on types and number of logic gates on one path,which is used to reduce the protected circuit paths.The algorithm classifies all paths by the number of every kind of logic gate and different influence of logic gates types on circuit aging,then removes the secure path of which aging will not occur,lessens the workload of circuit aging prediction,and improves the efficiency of aging prediction.