| 用于频率综合的电荷泵锁相环电路设计 |
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| 引用本文： | 冷思明,张海鹏.用于频率综合的电荷泵锁相环电路设计[J].杭州电子科技大学学报,2014(4):70-74. |
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| 作者姓名： | 冷思明 张海鹏 |
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| 作者单位： | 杭州电子科技大学电子信息学院,浙江杭州310018 |
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| 摘 要： | 在阐述了锁相环频率综合的工作原理、分析和设计方法的基础上,结合环路稳定性和相位噪声两方面因素对锁相环电路进行了建模及分析。采用安捷伦公司的ADS软件对锁相环进行了系统设计及仿真,并采用Cadence公司的Spectre-RF系列软件进行了锁相环具体电路设计和仿真。采用该方案设计的锁相环输出频率范围18.15 23 GHz,相位噪声-90 dBc/Hz,锁定时间小于5μs。
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| 关 键 词： | 锁相环 频率合成器 相位噪声 电荷泵 |
Design of Charge Pump PLL for Frequency Synthesizer |
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| Leng Siming,Zhang Haipeng.Design of Charge Pump PLL for Frequency Synthesizer[J].Journal of Hangzhou Dianzi University,2014(4):70-74. |
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| Authors: | Leng Siming Zhang Haipeng |
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| Affiliation: | (School of Electronics Information, Hangzhou Dianzi University, Hangzhou Zhejiang 310018, China) |
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| Abstract: | Basic concepts and fundamentals of PLL frequency synthesizer are proposed. This paper also shows the system design and analysis of PLL based on loop stability and phase noise optimal. ADS and Cadence Spectre-RF software was used to simulate and optimize the designed circuit. The output frequency of such kind of PLL is from 18.15 GHz to 23 GHz, phase noise is -90 dBe/Hz and locking time is less than 5μs. |
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| Keywords: | phase lock loop synthesizer phase noise charge pump |
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