A 9.5-Gb/s Si-bipolar ECL array |
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| Authors: | Tamamura M Shiotsu S Hojo M Nomura K Emori S Ichikawa H Akai T |
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| Affiliation: | Fujitsu Ltd., Kawasaki; |
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| Abstract: | A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed |
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