Efficient approaches to testing VHDL DSP models

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of this task. High level design tools are used to develop the test bench VHDL code. The test bench code models sensors which drive the Model Under Test (MUT). Data files which can also drive the MUT are prepared by environmental data generators. The system specification values are linked to the testbench via requirements capture tools and test plans. Intelligent interfaces are used to control the development and simulation of the test bench. The approach is applicable to the testing of any DSP system modeled in the VHDL language. It provides the modeler with the capability to rapidly test DSP models and adjust the model test environment to frequent changes in system requirements.Material in this paper was previously presented at the 1 st Annual RASSP Conference, Arlington, Virginia, August 16, 1994, at the 2nd Annual RASSP Conference, Arlington, VA, July 1995, and at the Spring 1995 VHDL International Users Forum in San Diego, CA.