基于Booth编码模乘模块RSA的VLSI设计

在Montgomery模乘算法基础上，采用大数乘法器常用的Booth编码技术缩减Montgomery模乘法的中间运算过程，将算法迭代次数为原来的一半，同时采用省进位加法器作为大数加法的核心，使模乘算法中一次迭代的延迟为两个一位全加器的延迟，提高了处理器的时仲频率，在0.25μm工艺下，对于1024位操作数，可在200MHz时钟频率下工作，其加密速率约为178kbit/s。

VLSI implementation of RSA cryptosystem based on the Booth-encoded montgomery module

The RSA public key crypto-system is a relatively safe technology, which is widely used in today's secure electronic communication. The RSA algorithm is a modular exponentiation algorithm and its core operation is modular multiplication. In this paper, the Booth-encoded technique that is commonly used in large integer multiplication is merged into the Montgomery modular multiplication algorithm. Using this algorithm, iteration number is reduced to about n/ 2 in each Montgomery operation. In addition, the carry saving adder is used as the core of the large integer addition and the delay of the iteration in modular multiplication is equated to the delay of two one-bit full adders. At a clock of 200?MHz, the encryption rate is about 178?kbit/s for 1?024-bit operands.