A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE |
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| Authors: | Hé ctor Solar [Author Vitae],Roc Berenguer [Author Vitae],Joaquí n de No [Author Vitae] [Author Vitae],Unai Alvarado [Author Vitae] [Author Vitae] |
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| Affiliation: | a CEIT, Manuel Lardizábal 15, 20018 San Sebastián, Spain
b Tecnun (University of Navarra), Manuel Lardizábal 13, 20018 San Sebastián, Spain |
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| Abstract: | A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P1 dB of 23.2 dBm and a PSAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors. |
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| Keywords: | CMOS Power amplifier IEEE 802.11a WLAN Power inductor |
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