A power efficient charge pump circuit configuration for fast locking PLL application |
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| Authors: | Saw Suraj Kumar Das Payali Maiti Madhusudan Majumder Alak |
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| Affiliation: | 1.Integrated Circuit and System (i-CAS) Lab, Department of Electronics and Communication Engineering (ECE), National Institute of Technology, Yupia, Arunachal Pradesh, 791112, India
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| Abstract: | Microsystem Technologies - One of the vital non-linearity issues that exists in a charge pump (CP) circuit is the current mismatch, which does not only reduce efficiency and increases latency, but... |
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