Enhancement of PMOS device performance with poly-SiGe gate |
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| Authors: | Wen-Chin Lee Watson B Tsu-Jae King Chenming Hu |
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| Affiliation: | Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA; |
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| Abstract: | Poly-Si and poly-Si0.75Ge0.25-gated PMOS transistors with a very thin gate oxide of 29 Å were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable Id-Vd characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on Vg, Tox, Vth and Vth. Both reduced GDE and superior hole mobility contribute to the enhanced performance |
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