| 基于SATA接口的并行扰码实现 |
| |
| 引用本文： | 陈序,杨龙,孟勇,卿粼波,何小海.基于SATA接口的并行扰码实现[J].电视技术,2013,37(19). |
| |
| 作者姓名： | 陈序 杨龙 孟勇 卿粼波 何小海 |
| |
| 作者单位： | 四川大学电子信息学院图像信息研究所,四川成都,610064 |
| |
| 基金项目： | 国家自然科学基金(61201388)，高等学校博士学科点专项科研基金(20110181120009) |
| |
| 摘 要： | 通过对SATA协议和扰码原理的分析,在串行扰码的基础上,实现了一种基于SATA接口的并行32 bit扰码和解扰算法.数据传输速度快、时延小、更稳定,并行扰码比串行扰码能更好地满足SATA接口的高速传输时序.最后在FPGA上使用VHDL语言编程,对模块进行了验证.
|
| 关 键 词： | SATA 扰码 解扰 并行算法 并行扰码 FPGA |
| 收稿时间： | 2013/2/16 0:00:00 |
| 修稿时间： | 2013/3/15 0:00:00 |
The Implementation of Parallel Scramble Based On SATA Interface |
| |
| Chen Xu,Yang Long,Meng Yong,Qin Linbo and He Xiaohai.The Implementation of Parallel Scramble Based On SATA Interface[J].Tv Engineering,2013,37(19). |
| |
| Authors: | Chen Xu Yang Long Meng Yong Qin Linbo and He Xiaohai |
| |
| Affiliation: | Sichuan university,Sichuan university,Sichuan university,Sichuan university,Sichuan university |
| |
| Abstract: | Based on the analysis of SATA protocol and scrambling code principle, implement a 32bit -parallel scramble and descramble algorithm for SATA interface from the serial scramble. Data transmission speed is faster and more stable, the time delay is small. The parallel scrambler can better meet the needs of the SATA interface for high-speed transmission timing than serial scrambler. Finally,using the VHDL programming language in the FPGA, the module was verified. |
| |
| Keywords: | SATA scramble descramble parallel algorithm parallel scramble FPGA |
| 本文献已被 万方数据 等数据库收录！ |
| 点击此处可从《电视技术》浏览原始摘要信息 |
|
点击此处可从《电视技术》下载全文 |
|
