一种多核指令集仿真器构建技术

为了提高指令集仿真器的速度并降低多核构造的复杂度, 提出了一种多核指令集仿真器的快速搭建技术。该技术结合了解释型、编译型以及混合仿真策略的优点, 通过预解码技术、可扩展单核结构、单核结构中的cache和TLB模拟机制以及多核调度机制的相互配合, 以实现多核的快速搭建。该技术已经成功应用于基于中国科学院微电子所自主研发的IME-Diamond多核DSP的四核仿真器ISD的搭建。复杂度分析与实验结果表明, 该技术复杂度低且能够提高仿真速度。

Technique for multi-core instruction-set simulator

In order to improve the simulation speed of multi-core instruction-set simulator (ISS) with low complexity, this paper presented a technique, which combined the advantages of interpretive strategy and compiled strategy, to form a multi-core ISS quickly. This technique used pre-decoder technique, extendable single core structure, cache and TLB simulation in single core, and the multi-core scheduling compatibly. This technique had been applied on forming multi-core simulator ISD, which was based on IME-diamond multi-core DSP processor. Complexity analysis and the experiment results show that this technique improves the simulation speed with low complexity.