一种高效通用的QC-LDPC译码器架构

基于软、硬件结合的方法，本文提出了一种高效通用的QC-LDPC译码器架构。该架构可以对不同码长、码率和校验矩阵结构的规则或非规则QC-LDPC码进行译码，支持Min-Sum近似及其改进译码算法，而且可以实现多种消息传递调度策略。通过将部分复杂的信息更新交由硬件加速器来完成，提高了译码吞吐量。针对QC-LDPC码校验矩阵：仁循环的结构，以块为单位对信息进行存储和处理。该架构还可以实现信息的并行处理，而译码器复杂度只有略微增加。

An Efficient General-Purpose Quasi-Cyclic LDPC Decoder Architecture

This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software.The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates,lengths and parity-check matrix structures,and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies.Some complicated message update is implemented by a hardware accelerator,thus the decoding throughput is improved.According to the quasi-cyclic structure of the parity-check matrix,the messages are stored and processed by blocks in decoding.Parallel message processing can also be realized with a small increase in implementation complexity.