Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates |
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Authors: | Ernesto Suarez Pik-Yiu Chan Murali Lingalugari John E. Ayers Evan Heller Faquir Jain |
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Affiliation: | 1. Electrical and Computer Engineering Department, University of Connecticut, 371 Fairfield Road, Storrs, CT, 06269-2157, USA 2. RSoft Design Group, Ossining, NY, USA
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Abstract: | This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells. |
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