一种基于QC-LDPC码的低复杂度分层迭代译码器

针对具有准循环结构的LDPC码,设计了一种低复杂度译码器。利用校验矩阵的循环特性以及分层迭代的译码算法,对一般的分层迭代架构进行改进,实现了译码器流水线处理,有效的减少迭代时间,提高吞吐量,最后针对码长为1200的LDPC码,基于FPGA平台Kintex7 xc7k325的芯片实现了该架构设计,结果表明,该译码器只消耗了100多个Slices和几块RAM,有效节省了硬件资源,同时译码时间比一般的分层架构减少了2/3左右,吞吐量提高了约2倍,研究成果具有重要的实用价值,可应用于资源有限的低速通信领域。

A Low-Complexity Layer-Iterative Decoder based QC-LDPC

In light of LDPC with quasi-cyclic structure, a low-complexity decoder is designed. Circulation of check matrix and layer-iterative decoding algorithm are applied to improving the common layer-iterative architecture,and thus achieving pipeline processing of decoder, and this could effectively reduce the iteration time and increases the throughput. Finally, based on FPGA platform of Kintex7 xc7k325 for LDPC with code length of 1200,the architecture design is realized. Results show that this decoder merely consumes over 100 Slice and several RAMs, thus effectively saving the hardware resource. In addition, the decoding time is only one third of that of the common architecture, while the throughput increases almost two times. The research is of important practical value, and the result could be applied to the low-speed communication field with limited resources.