| 卷积码Viterbi译码器的硬件实现 |
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| 引用本文： | 吴大雷,李兴江,袁东风.卷积码Viterbi译码器的硬件实现[J].信息技术与信息化,2001(4):35-37. |
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| 作者姓名： | 吴大雷 李兴江 袁东风 |
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| 作者单位： | 1. 山东大学信息科学与工程学院,济南,250100
2. 山东大学齐鲁医院,济南,250012 |
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| 摘 要： | 第三代移动通信系统标准中普遍采用卷积码和Turbo码作为信道编码方案.本文首先阐述了维特比译码算法,然后论述了(2,1,3)卷积码编码电路和维特比译码的单片机实现方案.最后把维特比算法与交织方案相结合,统计结果表明纠错性能有较大改善.
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| 关 键 词： | 卷积码 维特比译码 单片机 交织 |
| 修稿时间： | 2001年8月30日 |
The Hardware Implementation of Viterbi Decoder of Convolutional Codes |
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| WU Da-lei,LI Xing-jiang,YUAN Dong-feng.The Hardware Implementation of Viterbi Decoder of Convolutional Codes[J].Information Technology & Informatization,2001(4):35-37. |
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| Authors: | WU Da-lei LI Xing-jiang YUAN Dong-feng |
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| Affiliation: | WU Da-lei LI Xing-jiang YUAN Dong-feng |
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| Abstract: | Convolutional code and turbo code are universally used in the norm of the third generation mobile communication systems. This paper first expounds the principle of Viterbi algorithm. Then the coding circuit and the Viterbi decoding scheme of(2, l,3)convolutional code which are designed and implemented by single chip are discussed. Combining Viterbi algorithm with inter- leaving scheme, the statistics shows that the error-correcting performance of(2, 1, 3 ) convolutional code is improved greatly. |
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| Keywords: | Convolutional code Viterbi decoding Single chip Interleaving |
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