基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术；但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战；对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址；通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.

Embedded DRAM Memory BIST Design Based on SoC

Built-in Self Test(BIST) is an important technology in testing embedded memory of System-on-Chip(SoC).However,the embedded memory testing is still facing many challenges with several testing algorithm using BIST techniques.This paper presents an embedded DRAM memory BIST design based on SoC with several testing algorithm.The designed test circuit can reuse state of the state machine,and can generate operation commands using Cyclic Shift Register(CSR),and can generate the need addresses using the address generation circuit.The results show that the proposed embedded DRAM memory BIST design is a good compromise between the area overhead and the high fault coverage of the test circuit.