PVHArray:一种流水可伸缩的层次化可重构密码逻辑阵列结构

针对密码算法的高效能实现问题，该文提出了一种基于数据流的粗粒度可重构密码逻辑阵列结构PVHArray.通过研究密码算法运算及控制结构特征，基于可重构阵列结构设计方法，提出了以流水可伸缩的粗粒度可重构运算单元、层次化互连网络和面向周期级的分布式控制网络为主体的粗粒度可重构密码逻辑阵列结构及其参数化模型.为了提升可重构密码逻辑阵列的算法实现效能，该文结合密码算法映射结果，确定模型参数，构建了规模为4×4的高效能PVHArray结构.基于55nm CMOS工艺进行流片验证，芯片面积为12.25mm²，同时，针对该阵列芯片进行密码算法映射.实验结果表明，该文提出高效能PVHArray结构能够有效支持分组、序列以及杂凑密码算法的映射，在密文分组链接（CBC）模式下，相较于可重构密码逻辑阵列REMUS_LPP结构，其单位面积性能提升了约12.9%，单位功耗性能提升了约13.9%.

PVHArray:A Pipeline Variable Hierarchical Reconfigurable Cryptographic Logic Array Structure

Aiming at the high energy-efficiency implementation of cryptographic algorithm,this paper proposed a coarse-grained reconfigurable cryptographic logic array structure named PVHArray.Based on the research of cryptographic algorithm operation and control structure features,adopted the reconfigurable array structure design method,this paper proposed the coarse-grained reconfigurable cryptographic logic array structure and its parametric model,which is mainly composed of pipeline variable coarse-grained reconfigurable computing units,hierarchical interconnected network and periodic-oriented distributed control network.In order to improve the energy-efficiency of the reconfigurable cryptographic logic array,this paper combined the cryptographic algorithm mapping results to determine the model parameters,and constructed a high energy-efficiency PVHArray structure with a size of 4×4.The chip area of PVHArray is 12.25mm² based on 55nm CMOS technology,and at the same time,cryptographic algorithm mapping is performed for PVHArray.The experimental results show that the proposed high-efficiency PVHArray structure can effectively support the mapping of block,stream and hash cipher algorithm.In the cipher block chaining (CBC) mode,compared with state-of-the-art reconfigurable cryptographic logic array REMUS_LPP,the performance per unit area has increased by 12.9% and the performance per unit power has increased by 13.9%.