一种H.264/AVC帧内4x4预测算法的高效流水线结构

H.264编码器中的帧内4x4预测部分具有严重的数据依赖性，它的硬件化设计很难采用流水线实现，从而导致关键路径很长，硬件利用率很低，成为H.264编码器设计中的一个瓶颈。针对这个问题, 在不减少预测模式和不增加系统资源的的前提下，本文提出了一种新的结构，它通过利用原始像素进行模式判决和利用重构像素进行帧内预测的方法，可以使帧内预测与重构循环完全流水线实现，基本上达到了100%的硬件利用率，而且没有明显的PSNR的损失。本文所提出的硬件结构可在215个时钟周期内完成一个宏块的帧内4x4预测。用SMIC 0.13um工艺库综合，结果显示该结构最高可运行在250M，面积约为116K门，可支持4096x2160@30fps视频序列的实时编码。

An Efficient Pipelined Architecture for Intra 4x4 Prediction in H.264/AVC Encoder

There is extremely complicated data dependency and an immense amount of computation in H.264/AVC intra 4x4 coding algorithm. In order to avoid hardware waste and accelerate the speed of intra 4x4 coding, a novel hardware architecture for intra 4x4 coding is proposed in this paper. In this architecture, the original pixels are used to make mode decision(MD) and the reconstructed pixels are used to perform intra 4x4 prediction. The execution of intra prediction and reconstruction loop for all 4x4 blocks can be pipelined by adopting the strategy mentioned above. The hardware utilization can achieve nearly 100%. This design can perform intra 4x4 prediction for one macroblock in 215 cycles. And this architecture is synthesized using SMIC 0.13um library, the results show that the intra 4x4 coder needs only 116k gates and can working at 250 MHz, which can support the real-time coding of 4096x2160@30fps sequences.