A high-resolution CMOS time-to-digital converter utilizing aVernier delay line |
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Authors: | Dudek P. Szczepanski S. Hatfield J.V. |
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Affiliation: | Dept. of Electr. Eng., Univ. of Manchester Inst. of Sci. & Technol.; |
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Abstract: | This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-μm digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding ±1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable |
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