An evaluation of the systolic stack sequential decoder

The performance of a sequential stack decoder based on a new systolic priority queue is evaluated using extensive simulations over both memoryless Gaussian channels and Rayleigh fading channels. The results are used to determine interrelations between the decoder parameters, providing a simple way to design a systolic stack sequential decoder with an overall erasure probability approximately equal to the probability of a correct path overflow, while keeping the bit error rate of the decoder almost as low as that of the code. It is shown that this decoder circumvents some of the limitations inherent to usual stack decoders, while offering an increased decoding speed and being well suited for vlsi implementation.