di/dt Noise in CMOS Integrated Circuits |
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Authors: | Patrik Larsson |
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Affiliation: | (1) Bell Laboratories, Holmdel, NJ |
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Abstract: | This is an overview paper presenting di/dtnoise from a designer s perspective. Analysis and circuit designtechniques are presented taking package parasitics into account.The main focus is on digital CMOS design, but analysis and designsuggestions can easily be extended to mixed-mode design. |
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Keywords: | ground bounce di/dt noise simultaneous switching noise low-noise design |
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