利用参数稀疏性的卷积神经网络计算优化及其FPGA加速器设计

针对卷积神经网络(CNN)在嵌入式端的应用受实时性限制的问题，以及CNN卷积计算中存在较大程度的稀疏性的特性，该文提出一种基于FPGA的CNN加速器实现方法来提高计算速度。首先，挖掘出CNN卷积计算的稀疏性特点；其次，为了用好参数稀疏性，把CNN卷积计算转换为矩阵相乘；最后，提出基于FPGA的并行矩阵乘法器的实现方案。在Virtex-7 VC707 FPGA上的仿真结果表明，相比于传统的CNN加速器，该设计缩短了19%的计算时间。通过稀疏性来简化CNN计算过程的方式，不仅能在FPGA实现，也能迁移到其他嵌入式端。

Calculation Optimization for Convolutional Neural Networks and FPGA-based Accelerator Design Using the Parameters Sparsity

Concerning the problem of real-time restriction on the application of Convolution Neural Network (CNN) in embedded field, and the large degree of sparsity in CNN convolution calculations, this paper proposes an implement method of CNN accelerator based on FPGA to improve computation speed. Firstly, the sparseness characteristics of CNN convolution calculation are seeked out. Secondly, in order to use the parameters sparseness, CNN convolution calculations are converted to matrix multiplication. Finally, the implementation method of parallel matrix multiplier based on FPGA is proposed. Simulation results on the Virtex-7 VC707 FPGA show that the design shortens the calculation time by 19% compared to the traditional CNN accelerator. The method of simplifying the CNN calculation process by sparseness not only can be implemented on FPGA, but also can migrate to other embedded ends.