一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。

A Design of Digital-to-Analog Converter Based on 14-bit Successive Approximation Analog-to-Digital Converter

This paper describes a design of DAC based on 14-bit successive approximation ananlog-to-digital converter（SAR ADC）,which uses fully differential segmented capacitor array structure to reduce layout area.Thermal code control is used on sophomore-bit capacitorto improve the high bit capacitor＇s jump peak at the time of conversion and the monotoni-city ofDAC.Also,digital calibration technique is used based on the segmented capacitor arraystructure to reduce the mismatch between capacitors and improve the precision of SAR A-DC.Before calibrating,INL and DNL of SAR ADC reach to 10LSB and 4LSB respectively,as compared with pre-calibration,INL is not more than 0.5 LSB,and DNL not more th-an 0.6 LSB after calibrating.Results of simulation confirms that,DAC design in this paper greately improves p-erformance of SAR ADC.