28 nm多晶硅硬掩模刻蚀中的棒状颗粒缺陷与对策分析

在摩尔定律的影响下，半导体制造的线宽尺寸逐步到达极限。当前28 nm及以下工艺制程中，多晶硅栅极刻蚀普遍采用双层联动的硬掩模刻蚀加多晶硅刻蚀的方法，可以实现关键尺寸的有效控制，但同时也增加了颗粒缺陷的发生率。针对多晶硅硬掩模刻蚀(Polysilicon Hard Mask Etch, P1HM-ET)过程中出现的棒状颗粒缺陷，分析了缺陷的来源和形成机理。通过精准调控刻蚀结束后静电卡盘(Electrostatic-Chuck, ESC)对晶圆的释放时间和自身电荷的释放时间来加强刻蚀腔体内颗粒的清除和减小晶背静电吸附作用。结果显示，当晶圆释放时间增加2 s, ESC电荷释放时间增加6 s后，减少了约80%的棒状颗粒缺陷。通过调控相关联的工艺参数来减少缺陷，可以有效减少消耗性零件的使用，从而降低生产成本。

Analysis of Stick Particle Defect and Countermeasure in 28 nm Polysilicon Hard Mask Etching

Under the influence of Moore''s law, the linewidth size of semiconductor manufacturing gradually reaches its limit. In the current process of 28 nm and below, the polycrystalline silicon gate etching is generally adopted by double-layer linked hard mask etching and polycrystalline silicon etching, which achieve effective control of key dimensions and increase the incidence of particle defects. In this paper, the source and formation mechanism of stick particle defects in the process of hard mask etching of polysilicon are analyzed. The removal of particles in the etching cavity and the electrostatic adsorption of the crystal backside are enhanced by precisely adjusting the release time of electrostatic-chuck (ESC) on the wafer and the release time of its own charge after the etching. The results show that when the release time of the wafer is increased by 2 s and the release time of the ESC charge is increased by 6 s, the stick particle defects can be reduced by about 80%. By controlling the associated process parameters to reduce defects, the use of expendable parts and the production costs can be effectively reduced.