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The effect of thermal treatment on device characteristic and reliability for sub-100-nm CMOSFETs
Authors:Wen-Kuan Yeh Yean-Kuen Fang Mao-Chieh Chen
Affiliation:Electr. Eng. Dept., Nat. Univ. of Kaohsiung, Taiwan;
Abstract:The effect of post-thermal annealing after halo implantation on device characteristic and reliability of sub-100-nm CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced degradation. The best result of device performance and reliability was obtained by a post-thermal annealing treatment performed at medium temperatures (e.g., 900/spl deg/C) for a longer time (>1 min).
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