The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series |
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| Authors: | Chang J Ming Huang Shoemaker J Benoit J Szu-Liang Chen Wei Chen Siufu Chiu Ganesan R Leong G Lukka V Rusu S Srivastava D |
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| Affiliation: | Intel Corp., Santa Clara, CA; |
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| Abstract: | The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 mum2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures |
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