Optimized retrograde N-well for 1-/spl mu/m CMOS technology

Using experiment and simulation, transistors in a high-energy implanted N-well are designed for optimum device performance suitable for 1-/spl mu/m CMOS technology. The effect of process parameters on device performance is obtained. Superior body effect, junction capacitance, punchthrough voltage, and subthreshold slope are achieved for 1-/spl mu/m n- and p-channel transistors. With shallow P/P+ epitaxial material, this retrograde N-well approach also provides latch-up immunity for high-density CMOS.