基于FPGA和DDR的高效率矩阵转置方法

用可编程门阵列(FPGA)作为主处理芯片实现雷达信号处理时,大阶数矩阵转置经常由于双倍速率同步动态随机存储器(DDR)的跳行访问速率而成为系统处理速率的瓶颈。文中分析了DDR的读写机制,对DDR读写时间的组成进行了定量分析,提出了一种提高矩阵转置效率的分块式矩阵转置方法。该方法采用矩阵分块技术,使矩阵转置时DDR的读写速率得以均衡,从而提高DDR读写的平均效率。文中提供了矩阵转置效率的实验室实测数据,验证了该方法的有效性。该方法已在工程实践中得到了成功的应用。

High Efficiency Matrix Transposition Method Based on FPGA and DDR

In radar signal processing system using FPGA as the major processing chips, due to the low jump-row accessing rate of DDR, large-dimension matrix transposition often become the bottleneck of the system processing. This paper detailed analysis the access mechanism of DDR, and quantitatively analysis the composition of DDR access time, and presents a partitioning matrix transposition method to improve efficiency of matrix transposition. Using matrix partitioning technology, this method balances the access speed between DDR read and write during the matrix transposition process, thus improve the average efficiency of DDR access. Measurements data of matrix transposition efficiency through lab tests of DDR access are also provided to verify the validity of the method. The method has been applied successfully in engineering practices.