| Abstract: | In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-$hbox{cm}^{2}$ 11-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-${rm mu}hbox{m}$ CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of $8 {rm mu}hbox{m} times 8 {rm mu}hbox{m}$ pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness ($< hbox{0.01}$ mrad), the first level packaging of SLM die is done using specially designed SiC holders. To avoid trapped particles between the die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (less than or equal to one 0.8-${rm mu}hbox{m particle/cm}^{2}$ ) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary wafer- or zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123?648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.$hfill$2009-0169] |
