0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below